2.3GHz to 2.7GHz Wireless
Broadband RF Transceiver
Pin Description
PIN
1
2
3
4
NAME
V CCRXLNA
GNDRXLNA
B5
RXRF+
FUNCTION
LNA Supply Voltage. Bypass with a capacitor as close as possible to the pin.
LNA Ground
Receiver and Transmitter Gain-Control Logic Input Bit 5
LNA Differential Inputs. Inputs are internally DC-coupled. An external shunt inductor and series
5
RXRF-
capacitors match the inputs to 100
differential.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
B4
V CCTXPAD
B3
B2
TXRF+
TXRF-
B1
V CCTXMX
PABIAS
SCLK
CLOCKOUT
XTAL2
XTAL1
V CCXTAL
V CCDIG
V CCCP
GNDCP
CPOUT+
CPOUT-
ENABLE
GNDVCO
BYPASS
V CCVCO
DOUT
CS
DIN
RSSI
B7
B6
RXBBQ-
RXBBQ+
RXBBI-
RXBBI+
V CCRXVGA
RXHP
V CCRXFL
Receiver and Transmitter Gain-Control Logic Input Bit 4
Supply Voltage for Power-Amplifier Driver. Bypass with a capacitor as close as possible to the pin.
Receiver and Transmitter Gain-Control Logic Input Bit 3
Receiver and Transmitter Gain-Control Logic Input Bit 2
Power-Amplifier Driver Differential Output. PA driver output is internally matched to a 100
differential. The pins have internal DC-blocking capacitors.
Receiver and Transmitter Gain-Control Logic Input Bit 1
Transmitter Upconverter Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Transmit PA Bias DAC Output
Serial-Clock Logic Input of 4-Wire Serial Interface (See Figure 1)
Reference Clock Buffer Output
Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input.
Connection for Crystal-Oscillator Off-Chip Capacitors. When using an external reference clock
input, leave XTAL1 unconnected.
Crystal-Oscillator Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Digital Circuit Supply Voltage. Bypass with a capacitor as close as possible to the pin.
PLL Charge-Pump Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Charge-Pump Circuit Ground
Differential Charge-Pump Output. Connect the frequency synthesizer ’s loop filter between CPOUT+
and CPOUT-. (See the Typical Operating Circuit .)
Operation Mode Logic Input. See Table 1 for operating modes.
VCO Ground
On-Chip VCO Regulator Output Bypass. Bypass with a 1 μF capacitor to GND. Do not connect other
circuitry to this point.
VCO Supply Voltage. Bypass with a capacitor as close as possible to the pin.
Data Logic Output of 4-Wire Serial Interface (See Figure 1)
Chip-Select Logic Input of 4-Wire Serial Interface (See Figure 1)
Data Logic Input of 4-Wire Serial Interface (See Figure 1)
RSSI or Temperature Sensor Multiplexed Analog Output
Receiver Gain-Control Logic Input Bit 7
Receiver and Transmitter Gain-Control Logic Input Bit 6
Receiver Baseband Q-Channel Differential Outputs. In Tx calibration mode, these pins are the
LO leakage and sideband detector outputs.
Receiver Baseband I-Channel Differential Outputs. In Tx calibration mode, these pins are the
LO leakage and sideband detector outputs.
Receiver VGA Supply Voltage
Receiver Baseband AC-Coupling Highpass Corner Frequency Control Logic Input
Receiver Baseband Filter Supply Voltage
14
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